Job Description:

Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.

Job Responsibilities:

Excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs
RTL coding, modeling of analog blocks, and writing complex system-level testbenches in SystemVerilog
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
Debugging RTL and gate-level simulation failures
Firmware debug

Job Requirements/Qualifications:

The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems.
To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits and IP subsystems.
Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Seeking a highly motivated and innovative ASIC digital design engineer with strong theoretical and practical background in high-speed data recovery circuits.
Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products.
The position offers an excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs.