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ASIC Digital Design Engineering – Synopsys Student Intern Calgary

    Website Synopsys Inc

    Job Description:

    Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.

    Job Responsibilities:

    • Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them.
    • Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.
    • Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
    • The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems.
    • To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits and IP subsystems.
    • Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

    Job Requirements/Qualifications:

    • Excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs
    • RTL coding, modeling of analog blocks, and writing complex system-level testbenches in SystemVerilog
    • Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
    • Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
    • Debugging RTL and gate-level simulation failures
    • Firmware debug
    • Experience writing scripts in languages such as Perl and Unix shell
    • Familiar with Verilog and SystemVerilog

    To apply for this job please visit synopsys.ongig.com.


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